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SV51005
2014.01.10
PCLK Control Block
4-13
PCLK Control Block
To drive the HSSI horizontal PCLK control block, select the HSSI output or internal logic .
To drive the DPA horizontal PCLK, select the DPA clock output or internal logic. You can only use the DPA
clock output to generate the vertical PCLK to the core.
Figure 4-13: Horizontal PCLK Control Block for Stratix V Devices
HSSI Output or
DPA Clock Output
Internal Logic
Static Clock Select
Horizontal PCLK
External PLL Clock Output Control Block
You can enable or disable the dedicated external clock output pins using the ALTCLKCTRL megafunction.
Figure 4-14: External PLL Output Clock Control Block for Stratix V Devices
PLL Counter
Outputs
18
Static Clock Select
Enable/
Disable
Internal
Logic
When the device is in user mode,
you can only set the clock select
signals through a configuration file
The clock control block feeds to a multiplexer
within the FPLL_<#>_CLKOUT pin’s IOE. The
FPLL_<#>_CLKOUT pin is a dual-purpose pin.
Therefore, this multiplexer selects either an
internal signal or the output of the clock control
block.
IOE
Internal
Logic
Static Clock
Select
( .sof or .pof ); they cannot be
controlled dynamically.
FPLL_<#>_CLKOUT pin
Related Information
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
Provides more information about ALTCLKCTRL megafunction.
Clock Power Down
You can power down the GCLK and RCLK clock networks using both static and dynamic approaches.
When a clock network is powered down, all the logic fed by the clock network is in off-state, reducing the
overall power consumption of the device. The unused GCLK, RCLK, and PCLK networks are automatically
powered down through configuration bit settings in the configuration file ( .sof or .pof ) generated by the
Quartus II software.
Clock Networks and PLLs in Stratix V Devices
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